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HANBit
HSD16M32D4
Synchronous DRAM Module 64Mbyte(16Mx32-Bit), 100pin DIMM, 4Banks, 8K Ref., 3.3V Part No. HSD16M32D4
GENERAL DESCRIPTION
The HSD16M32D4 is a 16M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 2M x 16 bit x 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 100-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M32D4 is a DIMM( Dual in line Memory Module) and is intended for mounting into 100-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification HSD16M32D4-10 : 100MHz (CL=2) HSD16M32D4-10L : 100MHz (CL=3) HSD16M32D4-12 : 125MHz (CL=3) HSD16M32D4-13 : 133MHz (CL=3) * Burst mode operation * Auto & self refresh capability (8192 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * The used device is 4M x 16bit x 4Banks SDRAM
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HSD16M32D4
PIN ASSIGNMENT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Symbol Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQM0 Vss A0 A2 A4 A6 A8 A10 BA1 NC VCC NC NC NC CLK0 PIN 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VSS CKE0 /WE /CS0 /CS2 VCC NC NC NC NC VSS DQM2 DQ16 DQ17 DQ18 DQ19 VCC DQ20 DQ21 DQ22 DQ23 VSS SDA SCL VCC PIN 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Symbol VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 DQ13 DQ14 DQ15 DQM1 VSS A1 A3 A5 A7 A9 BA0 A11 NC VCC /RAS /CAS NC CLK1 PIN 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VSS CKE1 NC /CS1 /CS3 VCC NC NC NC NC VSS DQM3 DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SA0 SA1 SA2
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FUNCTIONAL BLOCK DIAGRAM
HSD16M32D4
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HSD16M32D4
PIN FUNCTION DESCRIPTION
PIN CLK /CS 0~3 NAME System clock Chip enable INPUT FUNCTION Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~DQ 32 VDD/VSS Data input/output Power supply/ground Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1V to 4.6V -1V to 4.6V 4W -55oC to 150oC
Short Circuit Output Current IOS 400mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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HSD16M32D4
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4 UNIT V V V V V 1 2 IOH = -2mA IOL = 2mA 3 NOTE
Input leakage current I LI -12 12 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23 C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Clock /RAS, /CAS,/WE,/CS, CKE, DQM Address DQ (DQ0 ~ DQ63) SYMBOL CCLK CIN CADD COUT MIN 20 20 20 32 MAX 32 40 40 52 UNITS pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70 C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current (One bank active) ICC1 tRC tRC(min) IO = 0mA ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= CKE VIH(min) Precharge standby current in non power-down mode ICC2N CS* VIH(min), tCC=10ns 64 mA 8 mA 8 mA 600 600 560 560 mA 1 -13 -12 -10 -10L VERSION UNIT NOTE
Precharge standby current in power-down mode
ICC2PS
Input signals are changed one time during 20ns
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CKE VIH(min) ICC2NS CLK VIL(max), tCC= 56
HSD16M32D4
Input signals are stable Active standby current in ICC3P ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), ICC3N CS*VIH(min), tCC=10ns 240 mA 24 mA 24
power-down mode
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tCC=
140
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 720 4Banks Activated tCCD = 2CLKs Refresh current Self refresh current ICC5 ICC6 tRC tRC(min) CKE 0.2V 840 840 20 8 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 800 800 mA mA mA 2 720 560 560 mA 1
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70 C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V Ns V
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HSD16M32D4
3.3V 1200 DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load DOUT Z0=50
Vtt=1.4V
50 50pF
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time SYMBOL -13 tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
UNIT -12 16 20 20 48 100 65 68 2 2 CLK + 20 ns 1 1 1 2 ea CLK CLK CLK 70 70 -10 20 20 20 50 -10L 20 20 20 50 ns ns ns ns ns ns CLK 15 20 20 45
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data
1 2.5
tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 -
2 2 3 4
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .
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AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -13 PARAMETER CAS 7.5 latency=3 CLK cycle time CAS latency=2 CAS 5.4 CLK to valid output delay latency=3 tSAC CAS latency=2 CAS 2.7 Output data hold time latency=3 tOH CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS 5.4 CLK to output in Hi-Z latency=3 tSHZ CAS latency=2 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter. 6 7 ns 6 6 6 ns 2 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 3 3 2 1 1 3 3 2 1 1 3 3 2 1 1 ns ns ns ns ns 3 3 3 3 3 3 3 ns 2 3 3 3 6 7 ns 1,2 6 6 6 10 12 tCC 1000 1000 1000 1000 ns 1 8 10 10 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX -12 -10 -10L UNIT NOTE
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SIMPLIFIED TRUTH TABLE
COMMAND Register Mode register set Auto refresh Refresh Self refresh Bank active & row addr. Read & column address Auto disable Auto disable Auto disable Auto disable Burst Stop Precharg e Bank selection All banks Entry Exit Entry Exit H H H L H L H H X H L X X L H L H L L H L X H L H L L L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X V X precharge precharge H X L H L L X V precharge precharge H X L H L H X V Entry Exit CKE n-1 H H L H CKE n X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1
HSD16M32D4
A10/ AP
A11 A9~A0
NOT E
OP code X X Row address L H Column Address (A0 ~ A8) Column Address (A0 ~ A8) H X L H X X
1,2 3 3 3 3
4 4,5
Write & column address
L
4
4,5 6
Clock suspend or active power down
Precharge power down mode DQM
X X V X X X 7
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12& BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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HSD16M32D4
PACKAGING INFORMATION
Unit : mm
Tolerances : 0.20 mm PCB Thickness: 1.27mm 0.10mm
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
MAX. frq CL2 100MHz CL3 100MHz CL3 125MHz CL 3 133MHz
HSD16M32D4-10 HSD16M32D4-10L HSD16M32D4-12 HSD16M32D4-13
64MByte
16M x 32 16M x 32 16M x 32 16M x 32
100 Pin-DIMM
8K 8K 8K 8K
3.3V 3.3V 3.3V 3.3V
SDRAM SDRAM SDRAM SDRAM
64MByte 64MByte 64MByte
100 Pin 100 Pin 100 Pin
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